module   recv_bit  
(
input						rst,
input						clk_400M	,
input						rx,
output	reg  			rx_bit,
output	reg			rx_bit_en,


output	reg			rx_r,
output	reg   		rx_rr,
output	reg			nrx_r,
output	reg			nnrx_r,
output	reg   		rx_rg,
output	reg  	 		rx_fg,
output	reg   		rx_dg	




);


wire 			rx_out;
reg  [1:0]  sample_count=0;


always@(posedge clk_400M or posedge rst)
if(rst) begin
	rx_r			<=0;
	rx_rr			<=0;
	nrx_r			<=1'b1;
	nnrx_r		<=0;
	rx_rg			<=0;
	rx_fg			<=0;
	rx_dg			<=0;

end
else begin
	rx_r			<=rx_out;
	rx_rr			<=rx_r;
	nrx_r			<=!rx_r;
	nnrx_r		<=!nrx_r;
	
	rx_rg			<= rx_r & nrx_r;  //rising edge
	rx_fg			<=nrx_r&nnrx_r;	//falling edge
	rx_dg			<=rx_r^rx_rr;    //double edge 
end




always@(posedge clk_400M or posedge rst)
if(rst)
    begin
        rx_bit_en    <=0;    
        rx_bit       <=0;
     end
else
   begin
        rx_bit_en<=0;  
		
			if(sample_count==2)
				begin
					rx_bit<=rx_r;
					rx_bit_en<=1'b1;
				end
          if(rx_dg)
            begin         
            sample_count<=0;
            end
          else 
				 begin
					 sample_count<=sample_count+1'b1;
						
					end
    end



 lvds_rx  lvds_rx_inst

 (
	.rx_in		(rx),
	.rx_out		(rx_out)
	);


endmodule
